1. Field of the Invention
The present invention relates to a method and a related circuit for phase splitting, and more specifically, to a method and a related circuit for phase splitting by phase interpolation according to multi-phase reference clocks.
2. Description of the Prior Art
In the modern information-oriented society, electronic apparatuses for processing and storing digital information require higher operating speeds and higher circuit densities. Accordingly, the precision of circuit control and operation becomes important. For instance, the timing control of a CD-ROM drive requires precise management. Although a CD-ROM drive can analyze light reflected from a CD to find a clock for synchronous time control, it requires a clock period to be divided into a plurality of different time points in order to control data write/access precisely. In addition, devices such as a time-to-digital converter (TDC) or a time delay calibration circuit also require clocks in different phases in order to divide the clock period into many time points. Therefore, a multiple phase generating circuit capable of dividing one clock into several clocks with the same frequency but different phases becomes indispensable.
In the prior art, clocks of the same frequency but different phases can be provided by each stage of inverters in a ring oscillator. Assuming that 16 clocks of the same frequency but different phases are required, and the phase difference of the clocks is distributed over 360 degrees, in the prior art, 8 differential inverters are needed in a ring oscillator so that 16 clocks of the same frequency but different phases can be provided at the two outputs of each inverter. Please refer to the FIG. 1 showing a ring oscillator 10 according to the prior art. The oscillator 10 has 8 inverters 12A–12H connected in a ring with two differential inputs and two differential outputs each. For instance, the inverter 12A receives two inverse outputs from the differential output s of the inverter 12H via its differential inputs, and the two inverse outputs from the differential outputs of the phase inverter 12A are inputted into the differential inputs of the inverter 12B. In such a manner 16 output clocks A-H, Ai-Hi of the same frequency but different phases can be generated by collecting the outputs from the differential outputs of the inverters 12A–12H. As shown in FIG. 1, the differential outputs of the inverter 12A generate output clocks B, Bi, the phase inverter 12B generates output clocks C, Ci. In the same way, the phase inverter 12H generates output clocks A, Ai. Taking the output clock A as 0 degrees, the phase difference of the output clocks are shown in FIG. 1. For instance, the output clocks A, Ai are output from the differential output of the inverter 12H, thus there is a phase difference of 180 degrees between the output clock Ai and the output clock A. Similarly, there is a phase difference of 45 degrees between the output clock C and the output clock A, and there is a phase difference of 225 (=45+180) degrees between the output clock Ci and the output clock A.
Please refer to FIG. 2 showing a waveform timing diagram of the output clocks A-H, Ai-Hi. The horizontal axis represents time, and the vertical axis represents waveform amplitude. In the ring oscillator, each inverter delays a signal at its inputs by a period of time and outputs signals inversely, and by connecting the phase inverters serially, output clocks of periodical oscillation can be obtained at the outputs of the inverters. For instance in FIG. 2, the output clock A falls from high level to low level at time point tp0 (while the output clock Ai rises from low level to high level at time point tp0). After delaying the output clocks A, Ai by the phase inverter 12A, the output clock B increases from low level to high level at time point tp0+Tg (while the output clock Bi increases from low level to high level), wherein Tg means the delay time of the inverter 12A. Similarly, after the output clocks B, Bi by the inverter 12B are delayed, the level change of the clocks C, Ci will be triggered at time point tp0+2Tg (assuming that each inverter has the same delay time Tg). Eventually the phase inverter 12G will trigger the level change of the clocks H, Hi at time point tp0+7Tg, and the inverter 12H will trigger the level change of the clocks A, Ai at time point tp0+8Tg and then oscillation starts. In other word, the total delay time 8Tg is a half of the period of an output clock, and the period or the frequency of an output clock can be changed by adjusting the delay time Tg. Since the delay time 8Tg is a half of the period of an output clock, the delay time 8Tg equals to a phase difference of 22.5 degrees. For instance in the phase inverter 12A, the output clock B, by adding the delay time (22.5 degrees) to the output clock A and reversing the output phase (180 degrees), has a phase difference of 202.5 (=22.5+180) degrees relative to the output clock A. Please refer to FIG. 3 showing another waveform timing diagram of the output clocks A-H, Ai-Hi, wherein the horizontal axis represents time, and the vertical axis represents waveform amplitude as in FIG. 2. However, FIG. 3 is made in sequence of phase difference with the output clock A. As shown in FIG. 3, based on a rising edge of the output clock A (e.g. a rising edge at time point tp1), the following rising edges (e.g. rising edges of the clocks Bi, C, H at time points tp1+Tg, tp1+2Tg, tp1+15Tg) can divide a period of the output clocks equally by 16 for the purpose of precise timing control. Such kind of division is equivalent to phase splitting.
However, there are several disadvantages in prior art. First, the ring oscillator requires a plurality of inverters, but at the same time the inverters may not be matched to each other causing noise. Such noise and mismatch cause jitter in each output clock or errors in phase difference. Please refer to FIG. 4 showing a waveform timing diagram of the output clocks in FIG. 1 in non-ideal conditions, wherein the horizontal axis represents time and the vertical axis represents waveform amplitude. If jitter exists in the output clock A, the duty cycle of each period of the output clock A is unstable. For instance, in period Tp1 from time point tp3 to time point tp4, the duty cycle is 50% and the high level signal is 180 degrees. However influenced by jitter, in period Tp2 from time point tp4 to time point tp5, the duty cycle may increase and the high level signal may become 185 degrees. In addition, the period of each output clock may be changed. For instance, the time period Tp1 may be different from the time period Tp2.
Furthermore, since the ring oscillator triggers level changes of inverters alternately, if the duty cycle of the output clock is unstable, the phase difference between the output clocks becomes unstable. As shown in FIG. 4, the rising edge of the output clock A at time points tp3, tp4 triggers the falling edge of the output clock B after the delay time Tg (equivalent to a phase difference of 22.5 degrees), and then the falling edge of the output clock B triggers the rising edge of the output clock C after the delay time Tg (equivalent to a phase difference of 45 degrees). Even if the output clock A does not have an ideal duty cycle in period Tp2, rising edges of each period of the output clock C keep a phase difference of 45 degrees (equivalent to 2Tg of delay time) with rising edges of each period of the output clock A. However, the rising edge of the output clock Bi is triggered by the falling edge of the output clock A at time points tp3b, tp4b, since the output clock A has unstable duty cycles in period Tp1, Tp2, the time when the falling edge occurs of the output clock A is accordingly unstable, so that the phase difference between the output clock B and the output clock A is also unstable. As shown in FIG. 4, the first rising edge after time point tp3 of the output clock B keeps an ideal phase difference of 202.5 degrees with the rising edge at time point tp3 of the output clock A due to an ideal duty cycle in period Tp1 of the output clock A. However in the case of the second rising edge of the output clock B, since the duty cycle between the rising edge and the falling edge in period Tp2 of the output clock A increases, the phase difference of the two rising edges of the output clocks A, B after time point tp4 increases to 207.5 degrees. Similarly, the phase difference between the rising edge and the falling edge of the output clocks A, B after time point tp5 decreases to 198.5 degrees. In other words, due to the instability of the duty cycle of the output clock, the phase difference of the rising edges of each output clock is accordingly unstable, so that a period cannot be divided equally as shown in FIG. 3.
Moreover, since the period of each output clock of the ring oscillator is in proportion to the sum of the delay time of the inverters, a plurality of inverters are required in order to generate a plurality of output clocks of the same frequency but different phases, and accordingly, the output clocks have a longer period. However, the period of the clock requires shortening in modern applications. In order to reduce the clock period, the ring oscillator requires a higher power to drive inverters to convert signal level rapidly to reduce the delay time Tg. However, this becomes a burden to the whole circuit.
In the prior art, in a ring oscillator many stages of inverters are required to generate output clocks of the same frequency with split phases. More inverters affect the feedback system of the ring oscillators and cause jitter, phase distortion, higher power consumption, and increased circuit complexity.